As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. Although the field effect transistor feature size is reducing with advances in process technology, even greater packing density can be achieved by forming transistors over insulating layers, such as oxide. These transistors are commonly referred to as "thin film transistors" (TFT).
With TFTs, a thin film of semiconductive material is first provided. A central channel region of the thin film is masked, while opposing adjacent source/drain regions are doped with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having an active channel region formed entirely within a thin film as opposed to a bulk semiconductor substrate.
The invention grew out of needs associated with TFTs and their usage in high-density static random access memories (SRAMs) and flat panel displays. A static memory cell is characterized by operation in one of two mutually exclusive and cell-maintaining operating states. Each operating state defines one of the two possible binary bit values, 0 or 1. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a "high" voltage to indicate a "set" operating state. The memory cell output produces a "low" voltage to indicate a "reset" memory cell operating state. A low or reset output voltage usually represents a binary value of 0, and a high or set output voltage represents a binary value of 1.
A static memory cell is said to be bi-stable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to operating states of the memory cell, as long as the memory cell receives power.
The operation of the static memory cell is in contrast to other types of memory cells, such as dynamic cells, which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than very short time periods. A dynamic memory cell has no feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift towards intermediate or indeterminate voltages, effectively resulting in loss of data.
Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. SRAM cell density can be maximized with three-dimensional integration. For example, load transistors of the SRAM cell constitute TFTs which are folded over the bulk transistors. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along a different path than has the design of dynamic memories.
Ongoing efforts in SRAM circuitry have brought about the development of TFTs in an attempt to minimize space and for other advantageous reasons associated with TFTs. While the invention grew out of needs associated with TFTs of SRAM circuitry, the artisan will appreciate applicability of the invention to other types of circuitry, for example, TFT based AMLCDs where a TFT can be used as a pass transistor in a pixel and also in the driver circuitry.
One common material utilized as the thin source, channel and drain film in a TFT is polysilicon. Such is comprised of multiple forms of individual single crystal silicon grains. The locations where two individual crystalline grains abut one another is commonly referred to as a grain boundary. Grain boundaries are inherent in polycrystalline materials, such as polysilicon, as it is the boundaries which define the breaks between individual crystal grains. The crystalline structure breaks down at the grain boundaries, giving rise to a high concentration of broken or "dangling" Si bonds. These dangling bonds "trap" carriers and give rise to potential barriers at the grain boundaries. These potential a barriers impede the flow of carriers in polysilicon, thus reducing conductivity compared to bulk silicon.
The grain boundary potential barrier height is proportional to the square of the dangling bond density, or "trap density". The smaller the grain size, the higher the trap density and thus the lower the conductance. In a TFT, the grain boundary potential barrier height in the channel is controlled by the gate voltage, and hence the conductivity is a function of the gate voltage. The TFTs, however, have a lower drive compared to bulk transistors because of lower mobility in the channel and higher V.sub.t due to the larger trap concentration.
The grain boundary trap concentration also affects the leakage current or the OFF current in TFTs. In polysilicon or other polycrystalline TFTs, the presence of grain boundary traps at the drain end can dramatically increase the leakage current and the presence of a "gate-to-drain" electric field. The increase in leakage results from either "thermionic field emission" and/or "Poole-Frenkel" emission through the grain boundary traps. Accordingly, the greater the number of grain boundaries (i.e., the smaller the grain size), the greater the current leakage through the material. Greater current leakage means that more power is required to replace the leaking current to maintain an SRAM cell transistor in its desired powered-on state. Such leakage is particularly adverse in laptop computers, where desired power consumption when a cell's state is not being changed would be desired to be very low to extend battery life.
High density SRAMs (16 Mb or higher) typically require TFTs with low OFF currents (&lt;50 fA) and high ON current (&gt;5 nA) in order to obtain acceptable low standby leakage and high memory cell stability. Current state-of-the-art TFTs provide low standby current at the expense of ON current, or at the expense of additional process complexity. One present way of minimizing this current leakage at the cost of increased process complexity is by providing a "lightly doped offset" (LDO) region within the thin film. A lightly doped offset region is an elongated region within the thin film which is positioned effectively between the channel region and the drain region and is not under direct gate control but is affected by the sole fringing fields. Such a region provides a buffer zone for the electric field between the channel and drain which minimizes leakage therebetween.
One prior art manner of contending with problems associated with grains boundaries is to "passivate" such boundaries after their formation. One technique involves exposing the thin film polycrystalline layer to atomic or plasma hydrogen, with the intent being to produce silicon-hydrogen bonds instead of dangling bonds at the boundary interfaces. An alternate technique is to implant F into the thin film polycrystalline layer in an effort to produce silicon-fluorine bonds at the boundary interfaces. A silicon-fluorine bond is much more desirable than a silicon hydrogen bond due to increased high temperature stability. However, the ion implantation technique of providing fluorine into a polycrystalline thin film is not without drawbacks. For example, the implantation undesirably damages the thin film layer and typically creates more dangling bonds inherent from the implantation process. It also is not particularly effective in putting the F at the grain boundaries where it is required.
Relatedly, literature reports have shown that it is possible to enhance the performance of thin film transistors, and particularly polysilicon thin film transistors, by using a drain offset region between the channel region and the drain region. The prior art literature reports provision of such layer to have a doping concentration identical to that of the channel region, or more preferably to have a dopant concentration of opposite conductivity type to that of the channel region and at a concentration less than that of the heavily conductively doped source and drain regions.
Prior art processes of producing thin film transistors with drain offset regions are described with reference to FIGS. 1-6. For example, FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a substrate 12. An insulating layer 13 is provided thereover, and includes an intervening or embedded electrically conductive transistor gate 14. That portion of substrate 12 immediately beneath layer 13 and gate 14 would comprise an insulator material. A gate dielectric layer 16 overlies insulating layer 13 and gate 14. Further, a thin film transistor layer 18 is provided over gate dielectric layer 16.
In accordance with prior art methods, thin film transistor layer 18 ii is subjected to a blanket implant, in this described example an n-type material, to some suitable first low concentration, such as 5.times.10.sup.17 ions/cm.sup.3 -5.times.10.sup.18 ions/cm.sup.3. The function of the blanket implant is to provide desired resultant semiconductivity for the channel region of the transistor.
Referring to FIG. 2, a mask 19 is provided over thin film transistor layer 18 to define a desired n- channel region 20 overlying gate 14. Wafer 10 is then subjected to p-type doping to provide an example p- implant concentration outside of mask 19 to provide an example p- concentration of from 5.times.10.sup.18 ions/cm.sup.3 5.times.10.sup.19 ions/cm.sup.3. The purpose of such implant is to overwhelm the concentration of the blanket n- implant previously provided to produce a desired drain offset region.
Referring to FIG. 3, channel region 20 and what becomes a desired drain offset region 24 are masked with a photoresist masking block 25. Wafer fragment 10 is then subjected to heavy p-type doping to provide a resultant p+ concentration of for example greater than or equal to 1.times.10.sup.20 ions/cm.sup.3. The result is provision of desired source and drain regions 26 and 27, respectively. The effect is to produce a lighter doped drain offset region of the same conductivity type of the source and drain regions.
An alternate prior art method of producing thin film transistors having drain offsets is described with reference to FIG. 4. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix "a", or with different numerals. FIG. 4 in this described embodiment depicts a processing step immediately subsequent to the FIG. 1 processing step of the first described embodiment. Here, a masking block 19a is patterned to overlap or extend laterally beyond the confines of gate 14 to provide a source offset region 17 and a drain offset region 24a. The wafer is then subjected to heavy p+ doping to produce the illustrated source and drain regions 26a and 27a, respectively. Therefore in accordance with this described prior art embodiment, the resultant drain offset region 24a is provided to be of the same identical concentration and conductivity type as that of channel region 22.
Yet another alternate prior art embodiment and method are shown in FIGS. 5 and 6. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix "b" or with different numerals. FIG. 5 illustrates a wafer fragment 10b shown at a processing step immediately subsequent to that depicted by FIG. 1 of the first described embodiment. Here, a photoresist masking layer 19b is patterned to provide a contact opening 21 effective for producing a desired drain offset region 24. The wafer fragment is then subjected to light p-type doping, yet to a concentration sufficient to overwhelm the n- concentration previously provided in drain offset region 24 by the FIG. 1 blanket implant.
Referring to FIG. 6, masking block 25 is provided and the wafer subjected to p+ doping to effectively produce the same resultant prior art construction of FIG. 3.
This invention concerns improved methods of forming thin film transistors having drain offsets as well as to an improved thin film transistor construction.